Design collection for multiprocessor embedded systems. Topics embody memory-usage determination as well as timing research of multi-threaded embedded program upon multi-core processors. Future generations of embedded systems will run multi- tasking program upon multi-processor platforms for low energy-consumption as well as tall opening.

In such systems, program tasks might share not usually processor cores though additionally caches as well as mental recall blocks, as well as a bandwidth for entrance to a mental recall hiearchies. This plan is to investigate a formidable interplay in between multi-threaded program as well as multi- guess units in hardware. One of a goals is to rise epitome models to steadily constraint a behaviours of hardware resources, multi-thread tasks, mechanisms for apparatus government as well as their interactions.

Such models will be used to guess memory-usage as well as worst-case reply times of particular tasks. A starting points of a plan will be UPPAAL as well as TIMES grown during the dialect for timing research formed upon model-checking, as well as classical analytic techniques such as RMA for schedulability research formed upon worst-case scenarios. One probable result is to mix these techniques with indication checking to grasp some-more accurate as well as scalable research.

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